digital Lab report


Write a lab report (due in one week) describing what you did, what you learned about FPGAs and VHDL development. In your report, make sure to answer the following questions:


  • Describe FPGAs as you would to the management of a company you work for, if you had been asked to evaluate them for possible use. What kinds of projects could make use of FPGAs? (Your manager is an executive, not an engineer.)

o Would you recommend FPGAs for prototyping? Why or why not?

o Would you recommend them for small-scale production runs?

Why or why not? What factors would influence this decision?

o Your company is bidding on a contract to make ten million mp3 players, but they each need to be as inexpensive as possible.

  • Would you recommend developing the code in VHDL?

    Why or why not?

  • If so, would you recommend using an FPGA in the design?

    Why or why not?

  • Describe the circuit that you programmed for this lab.

o What does it do? Does it seem to work correctly?

o How many digital inputs and outputs does it have?

o Could it be made more efficient? If so, how?


  • Look at the Boolean equations in the VHDL code.

o How many gate equivalents does it use (AND, OR, and NOT)?

o If this were implemented on a small FPGA (of 100,000 gates),

what percentage of its capacity would be used?

(Show your calculations.)


  • What is code reuse? How did we use it in Exercise 2?

o How much faster did you complete Exercise 2 than Exercise 1?

This is largely a result of not having to “re-invent the wheel.”

o Assume that your time costs your employer $50 per hour, and that you work forty hours a week on VHDL development. How much money per week, on average, would a similar speedup in development time save?












EET 205

Digital Electronics



Lab # 5

An Introduction to VHDL (and FPGAs)







“You tell a microprocessor what to do.
You tell an FPGA what to be.”

— (Original source unknown)




“Any sufficiently advanced technology is
indistinguishable from magic.”

–Arthur C. Clarke



Become familiar with the use of VHDL to configure FPGA devices into useful digital combinatorial circuits, based on Boolean Logic descriptions of circuit behavior.

Become familiar with re-use of VHDL code.

In this lab, we will be creating a VHDL description of a seven-segment decoder, and implementing this on a BASYS2 FPGA development board (“dev board.”) A seven-segment decoder takes a four-bit input and produces seven output signals – one for each of the LEDs in a seven-segment numerical display. With the correct definition, this decoder will translate the binary input combinations 0000, 0001, 0010 … 1101, 1110, 1111 into sixteen combinations of output signals (“a” through “g”) which will produce the correct visible digits on the built-in seven-segment display. For example, when presented with the input “0111,” the circuit should light up the LEDs at the top, top right, and bottom right of the display to produce a visible “7”.

The resulting circuit will implement seven four-variable Boolean functions. Six of these will be provided for you, in the interest of saving time. You will determine and construct the seventh function (for the center LED segment: “g.”)

The connections for the input switches and seven-segment display, hard-wired into the BASYS2 dev board, are shown in the BASYS2 board manual (see PDF.) The manual also shows the designation scheme for the seven segments.

Finally, we will re-use this code in a second, similar project – a hex counter. Re-use of known-good code, whether in C, Java, Python, VHDL, or another language, is an important part of software development. Without it, the creation of complex pieces of software would be essentially impossible.


Exercise 1: A seven-segment display in VHDL

  • Connect the BASYS2 board to the PC and turn on the power to the board.
  • Launch Xilinx ISE Project Navigator. If a project is open, close it.
  • Click File -> New Project
  • Call the project seven_segment
    • Leave the Location and Working directory options as-is
    • The top-level source type should be HDL



  • Use the following choices for the Project Settings page:
    • Evaluation Development Board: None Specified
    • Product Category: All
    • Family: Spartan3E
    • Device: XC3S100E (or XC3S250E – ask me)
    • Package: CP132
    • Speed: -4
    • Top-level Source Type: HDL   (if not set, back up one page)
    • Synthesis tool: XST (VHDL / Verilog)
    • Simulator: ISim (VHDL / Verilog)
    • Preferred Language: VHDL
    • Property Specification…: Store all values
    • Manual Compile Order: (unchecked)
    • VHDL Source Analysis Standard: VHDL-93
    • Enable Message Filtering: (unchecked)

Figure 1. The Project Settings dialog box

  • Click Next, then Finish.
  • In the Hierarchy window at the upper left, right-click on
    the xc3s100e-4cp132 (or xc3s250e-4cp132)
  • Select “New Source…”
  • Select “VHDL Module” and enter “sevenSeg” as the File name. Click Next.

Figure 2. The New Source Wizard opening dialog box.


  • In the Define Module screen, set up the following:
    • Port Name Direction         Bus      MSB    LSB
    • ——————————————————-
    • input in                     X         3          0
    • LED_A out
    • LED_B out
    • LED_C out
    • LED_D out
    • LED_E out
    • LED_F out
    • LED_G out

Figure 3. The port assignments for this project.


  • Click Next, then Finish. Xilinx ISE should create a skeleton file for your decoder.



  • Locate the section of the file that says:

architecture Behavioral of sevenSeg is

end Behavioral;

Figure 4. The “architecture” section of the code.

Hint: To save time, you can open the Word version of this lab from BB Learn and copy and paste the VHDL code into your project.

  • Just after the “architecture Behavioral of sevenSeg is” line (but before the “begin” line that follows it), add VHDL code to set up four Boolean signals to break out the inputs into easily-used names, as well as seven signals to hold temporary values for the LED lines (we’ll see why later):

SIGNAL a, b, c, d : STD_LOGIC;
SIGNAL temp_a, temp_b, temp_c, temp_d, temp_e, temp_f, temp_g : STD_LOGIC;

  • Between the “begin” and the “end Behavioral;” lines, add VHDL code to break the four-bit “input” vector out into four terms (A, B, C, and D). Here is the code to add:

a <= input(3);
b <= input(2);
c <= input(1);
d <= input(0);

  • After those lines, we need to add in the VHDL code to actually perform the Boolean logic which will translate the four-bit input into the seven-segment output. Each of the output variables will be assigned based on a Boolean equation. You can either use the straightforward sum-of-products version, or use any minimized solution that you discover. Here is the example for LED_A. It represents the topmost LED segment, and should be ON for input values 0, 2,3, 5, 6, 7, 8, 9, A, C, E, and F (since the LED representation of those digits uses the top LED on.) It should be off for input values 1, 4, b, and d (since those digits should have the top LED off.)

The Karnaugh map for this line is therefore (lowercase denotes negation):

+ Ad
Figure 5. The K-map for the logic for LED segment “a.”
(acually, one term isn’t needed. Can you tell which one?)


Therefore, the VHDL code for Segment A is:

temp_a <=   (not a and c) or (b and c) or
(not b and not d) or (c and not d) or
(a and not b and not c) or

(not a and b and d) or (a and not d);


Likewise, the VHDL code for Segment B through Segment F is:
temp_b <=   (not a and not b) or (not b and not d) or

(not a and not c and not d) or

(not a and c and d) or (a and not c and D);


temp_c <=   (a and not b) or (not c and d) or

(not a and not c) or (not a and d) or

(not a and b and c);


temp_d <=   (a and not c) or (a and not b and d) or

(not a and not b and not d) or

(not b and c and d) or

(b and c and not d) or (b and not c and d);


temp_e <=   (not b and not d) or (a and b) or

(c and not d) or (a and c);


temp_f <=   (not c and not d) or (a and not b) or

(not a and b and not c) or (b and not d) or

(a and c);


Finally, you need to develop the equation for Segment G (the segment in the center), and enter it in the VHDL code as temp_g. (Don’t forget the semicolon at the end.)


temp_g  <= (Your Boolean code for Segment G goes here.)        ;


Hint: use this process to determine the equation for segment “g”…

  • Make a 4-input (16-line) truth table, with inputs a, b, c, and d.
  • For all 16 digits, determine if the middle LED segment should be lit or not.
    (Examples: for “1” and “7,” it should be off. For “5” and “8,” it should be on.)

Remember that the hex digits “b” and “d” are lowercase, so they can be distinguished from “8” and “0.” Segment “g” should be on for both of these.

  • Make a 4-variable K-map from your truth table and find the groupings.
  • From the K-map, minimize the equation for segment “g” and write the code.

Figure 6. The Boolean logic for all segments except “g”. (You do that one.)


  • Next, we need to invert these signals and connect them to the output lines from our decoder. (This is because the LED display on the BASYS board uses
    active-low signals — in other words, a particular LED segment is lit up when its signal is low, not high.) Insert the following code to invert the signals:

LED_A <= not temp_a;
LED_B <= not temp_b;
LED_C <= not temp_c;
LED_D <= not temp_d;
LED_E <= not temp_e;
LED_F <= not temp_f;
LED_G <= not temp_g;
(This code should go just before the “     end Behavioral;    ” line.)

  • Save your code and double-click on “Synthesize – XST” in the left-hand window.
    • Wait for a minute or so; the compiler can take a while to work.
    • Does your code synthesize without errors?
      Congratulations; this almost NEVER happens!
    • If you have errors, try to figure out the reason by reading the error message. If you’re stuck, ask for help.
  • Once your code synthesizes correctly, it’s time to create the “constraints” file. This file contains restrictions that the final design must meet, including timing and routing specifications. For now, we’re not concerned about timing — but since the connections from the FPGA to the switches and LEDs are hardwired into the board, it’s important that we tell the software to connect these to the right pins.
    • Click on the “+” next to “User Constraints” in the Processes window.
    • Double-click on the “I/O Pin Planning (PlanAhead) – Pre-Synthesis” link (This is the first of the two “I/O Pin Planning” links)
    • A pop-up window will say that a UCF file needs to be created. Click Yes.
    • Eventually (be patient!), the PlanAhead application should launch.

Figure 7. The “Processes” window, showing the Pre-Synthesis link.


  • Now to make the connections. Once PlanAhead has loaded completely, you should see a representation of the FPGA device package in the “Package” window. (It’s three rings of pins surrounding an empty black space in the center. This represents an X-ray, top-down view of the small FPGA chip in the center of the BASYS2 board. All of the 132 connections are pads underneath the chip.)
    • In the “I/O Ports” window, click the “+” to expand the “input(4)” selection. This should split into input(0), input(1), input(2), and input(3).
    • Click on the “input”(4)” line, and wait a moment. The entire section (five lines) should be highlighted in blue. (If this doesn’t happen, wait a few seconds and click on it again.)

Figure 8. The PlanAhead application, showing the Input ports highlighted.

  • Once the “input” section is highlighted in blue, right-click it and choose “Place I/O Ports Sequentially”. (See Figure 9, below.)
  • Move the cursor over the FPGA outline in the Package window. You should now be placing the connection for input(0). Click on Pin P11 to make this connection.
  • You will now be placing input(1). Click on Pin L3 to make this connection.
  • Similarly, connect input(2) to K3.
  • Connect input(3) to B4.

Figure 9. The context (right-click) menu, showing the
“Place I/O Ports Sequentially” option.

  • Next, click, then wait, then click on the “Scalar ports(7)” line until it is highlighted.
  • Right-click the highlighted “Scalar ports(7)” line, and choose “Place I/O Ports Sequentially.”



  • Make the following connections. This step is needed to tell the compiler where the LEDs are physically wired to, on the BASYS2 board. For example, LED segment A is physically wired to pin L14 on the FPGA chip.

LED_A goes to L14;
LED_B goes to H12;
LED_C goes to N14;
LED_D goes to N11;
LED_E goes to P12;
LED_F goes to L13; and
LED_G goes to M12.


  • Click the floppy disk icon to save this configuration, then click the “X” in the upper right to close out of PlanAhead.
  • Switch back to the Xilinx ISE and double-click “Generate Programming File”.
  • If all goes well (you get a green check mark next to “Generate Programming File,” the next step is programming the board…
    • Turn on the power to the board, and make sure it is connected via USB.
    • Pull up Digilent Adept (the programmer for the Digilent board.)
    • Click on the Config tab.
    • Next to the PROM listing, click on Browse…
    • Browse to the sevenseg.bit file in your FPGA project directory,
      and select it.
    • Click “Program” and wait for the process to finish.
    • Power-cycle the board (so the FPGA loads the program from Flash.)

Your code should be on the board. Test it out and see if it works! (Work through all sixteen switch combinations to make sure the displays look right.)


Note: All four displays will activate unless you modify the display selectors.
This is normal (meaning, we won’t worry about it for now.)


Exercise 2: Re-use of VHDL code


Make sure your code from Exercise 1 works correctly for all 16 input combinations.


Click File -> New Project. Name the new project “HexCounter”.


Click Next, then Next, then Finish to complete the project wizard.


Right-click on the xc3s100e (or xc3s250e) and select “add copy of source”


Navigate up one directory, then into the SevenSeg directory you used for Exercise 1.


Select SevenSeg.vhd and SevenSeg.ucf (use ctrl-click to select the second one.)


Click Open, then OK.


Double-click on sevenSeg – Behavioral (sevenSeg.vhd) in the Hierarchy window.


Near the top of the file, under the “use IEEE.STD_LOGIC_1164.ALL;” line, add:

use ieee.std_logic_unsigned.all;  (VHDL doesn’t automatically know if logic vectors – strings of bits – are supposed to be signed or unsigned. This is telling it that we will use unsigned numbers in this project.)


Delete the “input:” line in the entity declaration, and replace it with:

clock: in STD_LOGIC; This gives us a signal to connect to an external clock.


Next, we need to generate a counter to slow down the incoming 50MHz clock signal to something slow enough to use to increment the count so we can see it. A 28-bit counter should be about right; this will divide the clock by 2^28, allowing us to see the numbers transition from 0 to 1 to 2 etc.


In the same section as the two SIGNAL declarations, add:

SIGNAL counter: STD_LOGIC_VECTOR(27 downto 0);


Now, we need to add some code to increment this count whenever the clock rises. We can do this by checking for a high clock level and checking for a “clock event” (or change.)  Just under “begin”, add this code:

process (clock)


if (clock = ‘1’ and clock’event) then

counter <= counter + 1;

end if;

end process;



We won’t be using the input switches for this exercise. Instead, we will use the highest four bits of the counter to generate the count.
Remove the code section that assigns a, b, c, and d. Replace it with:

a <= counter(27);

b <= counter(26);

c <= counter(25);

d <= counter(24);


Save the file and double-click on Synthesize – XST. You should get a green check mark. If not, check what errors are listed and fix them. Ask for help if you’re stuck.


Next, we need a connection to the on-board clock. Expand “User Constraints”, and double-click on Pre-Synthesis. Kick back and chill while PlanAhead slowly loads…


You will get an error message about invalid constraints. This is normal (after all, we removed the input lines going to the switches, so those signals are no longer defined.)


Expand the “Scalar ports(8) section in the I/O Ports window in the middle of the screen. All of the ports should still be assigned except for the new “clock” signal. (This is why we included the .ucf file from the last project!)


According to the BASYS2 manual, the clock is connected to pin B8. Drag the “clock” signal from the I/O Ports window onto pin B8 above. When the tooltip text says “Place clock at B8,” release it. Save and exit from PlanAhead.


Finally, we need to remove the old references to the “input” pins. Double-click on the “sevenSeg.ucf” file. Delete the references to the “input” signals. Save the file and close it (there is an X on its tab near the middle of the screen.)


Click on “sevenSeg – Behavioral(sevenSeg.vhd) in the Design window.


Double-click on “Generate Programming File,” and wait for the software to do its thing.

Figure 10. should be required reading for every engineer.
Switch to the Digilent Adept software. Click the Browse button next to “PROM” and browse to the new .bit file (up one directory, in the HexCounter directory.)


Click Program, then power-cycle the BASYS2 board and watch it run.


Write a lab report (due in one week) describing what you did, what you learned about FPGAs and VHDL development. In your report, make sure to answer the following questions:


  • Describe FPGAs as you would to the management of a company you work for, if you had been asked to evaluate them for possible use. What kinds of projects could make use of FPGAs? (Your manager is an executive, not an engineer.)
    • Would you recommend FPGAs for prototyping? Why or why not?
    • Would you recommend them for small-scale production runs?
      Why or why not? What factors would influence this decision?
    • Your company is bidding on a contract to make ten million mp3 players, but they each need to be as inexpensive as possible.
      • Would you recommend developing the code in VHDL?
        Why or why not?
      • If so, would you recommend using an FPGA in the design?
        Why or why not?
  • Describe the circuit that you programmed for this lab.
    • What does it do? Does it seem to work correctly?
    • How many digital inputs and outputs does it have?
    • Could it be made more efficient? If so, how?


  • Look at the Boolean equations in the VHDL code.
    • How many gate equivalents does it use (AND, OR, and NOT)?
    • If this were implemented on a small FPGA (of 100,000 gates),
      what percentage of its capacity would be used?
      (Show your calculations.)


  • What is code reuse? How did we use it in Exercise 2?
    • How much faster did you complete Exercise 2 than Exercise 1?
      This is largely a result of not having to “re-invent the wheel.”
    • Assume that your time costs your employer $50 per hour, and that you work forty hours a week on VHDL development. How much money per week, on average, would a similar speedup in development time save?



Place Similar Order Now!

  • Our Support Staff are online 24/7
  • Our Writers are available 24/7
  • Most Urgent order is delivered with 6 Hrs
  • 100% Original Assignment Plagiarism report can be sent to you upon request.